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<title>PTWRITE - Write Data to a Processor Trace Packet </title></head>
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<h1>PTWRITE - Write Data to a Processor Trace Packet</h1>
<table>
<tr>
<td>
<p><strong>Opcode/Instruction</strong></p>
<p>F3 REX.W 0F AE /4 PTWRITE <em>r64/m64</em></p>
<p>F3 0F AE /4 PTWRITE <em>r32/m32</em></p></td>
<td>
<p><strong>Op/En</strong></p>
<p>RM</p>
<p>RM</p></td>
<td>
<p><strong>64/32 bit Mode Support</strong></p>
<p>V/N.E</p>
<p>V/V</p></td>
<th>CPUID Feature Flag</th>
<td>
<p><strong>Description</strong></p>
<p>Reads the data from r64/m64 to encod into a PTW packet if dependencies are met (see details below).</p>
<p>Reads the data from r32/m32 to encode into a PTW packet if dependencies are met (see details below).</p></td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:rm (r)</td>
<td>NA</td>
<td>NA</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>This instruction reads data in the source operand and sends it to the Intel Processor Trace hardware to be encoded in a PTW packet if TriggerEn, ContextEn, FilterEn, and PTWEn are all set to 1. For more details on these values, see <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C</em>, Section 36.2.3, “Power Event Tracing”. The size of data is 64-bit if using REX.W in 64-bit mode, otherwise 32-bits of data are copied from the source operand.</p>
<p>Note: The instruction will #UD if prefix 66H is used.</p>
<h2>Operation</h2>
<pre>IF (IA32_RTIT_STATUS.TriggerEn &amp; IA32_RTIT_STATUS.ContextEn &amp; IA32_RTIT_STATUS.FilterEn &amp; IA32_RTIT_CTL.PTWEn) = 1
    PTW.PayloadBytes ← Encoded payload size;
    PTW.IP ← IA32_RTIT_CTL.FUPonPTW
    IF IA32_RTIT_CTL.FUPonPTW = 1
         Insert FUP packet with IP of PTWRITE;
    FI;
FI;</pre>
<h2>Flags Affected</h2>
<p>None.</p>
<h2>Other Exceptions</h2>
<table class="exception-table">
<tr>
<td>#GP(0)</td>
<td>If a memory operand effective address is outside the CS, DS, ES, FS or GS segments.</td></tr>
<tr>
<td>#SS(0)</td>
<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr>
<td>#PF (fault-code)</td>
<td>For a page fault.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If an unaligned memory reference is made while the current privilege level is 3 and alignment checking is enabled.</td></tr>
<tr>
<td>#UD</td>
<td>
<p>If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.</p>
<p>If LOCK prefix is used.</p>
<p>If 66H prefix is used.</p></td></tr></table>
<h2>Real-Address Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#GP(0)</td>
<td>If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.</td></tr>
<tr>
<td>#SS(0)</td>
<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr>
<td>#UD</td>
<td>
<p>If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.</p>
<p>If LOCK prefix is used.</p>
<p>If 66H prefix is used.</p></td></tr></table>
<h2>Virtual 8086 Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#GP(0)</td>
<td>If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.</td></tr>
<tr>
<td>#SS(0)</td>
<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr>
<td>#PF (fault-code)</td>
<td>For a page fault.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If an unaligned memory reference is made while alignment checking is enabled.</td></tr>
<tr>
<td>#UD</td>
<td>
<p>If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.</p>
<p>If LOCK prefix is used.</p>
<p>If 66H prefix is used.</p></td></tr></table>
<h2>Compatibility Mode Exceptions</h2>
<p>Same exceptions as in Protected Mode.</p>
<h2>64-Bit Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#GP(0)</td>
<td>If the memory address is in a non-canonical form.</td></tr>
<tr>
<td>#SS(0)</td>
<td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr>
<tr>
<td>#PF (fault-code)</td>
<td>For a page fault.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
<tr>
<td>#UD</td>
<td>
<p>If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.</p>
<p>If LOCK prefix is used.</p>
<p>If 66H prefix is used.</p></td></tr></table></body></html>